The present invention is directed, in general, to an integrated circuit and, more specifically, to a semiconductor device having a buried layer for reducing latchup, and a method of manufacture therefor.
Integrated circuits are well known and are extensively used in various present day technological devices and systems, such as sophisticated telecommunications and computer systems of all types. As the use of integrated circuits continues to grow, the demand for more inexpensive and improved integrated circuits also continues to rise. Thus, presently, an emphasis in the integrated circuit industry is to provide higher density, faster devices at a competitive price.
Complementary metal oxide semiconductor (CMOS) devices are some of the above-mentioned devices wherein there is currently an emphasis placed upon increasing both speed and density. Increasing the density of CMOS devices, however, tends to create undesirable parasitic bipolar transistors, which can latch-up the CMOS devices, drawing high current.
Bipolar parasitic transistors are generally formed when doped regions of two metal-oxide semiconductor (MOS) transistors are positioned very close together. A parasitic pnp bipolar transistor may be formed when a source/drain region of a P-channel MOS (PMOS) device acts as an emitter, a well of an adjacent N-channel MOS (NMOS) device acts as a base, and a P-type doped substrate acts as the collector. Alternatively, a parasitic npn bipolar transistor may be formed when a source/drain region of the NMOS device acts as an emitter, a substrate tie of the NMOS device acts as a base, and the well of the NMOS device acts as the collector.
Turning to Prior Art FIG. 1, illustrated are resistances Rs1, Rs2, Rw1, Rw2 that may arise in conventional CMOS devices 100, in conjunction with the bipolar parasitic transistors. The resistances, in particular resistances Rs1 and Rw1 that form across emitter base junctions, tend to cause latch-up by turning on the parasitic bipolar transistors.
Turning to Prior Art FIG. 2, with continued reference to FIG. 1, depicted is a circuit 200, which more clearly illustrates the resistances Rs1, Rs2, Rw1, Rw2. If enough current is being drawn through the resistances Rs1, Rs2, Rw1, Rw2 to force the parasitic bipolar transistor on, and a gain of a resistance loop 210 is greater than 1, the CMOS devices 100 tend to latch-up and begins to pull a large amount of current. This is an undesirable effect that may load down the power supply, stop circuit functionality, or destroy the CMOS devices 100.
Accordingly, what is needed in the art is a CMOS device and a method of manufacture therefor that does not experience the problems experienced by the prior art CMOS devices. A CMOS device that does not experience the latch-up problems associated with the parasitic bipolar transistors, is particularly desirable.
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device may include a well doped with a P-type dopant located over a semiconductor substrate. The semiconductor device may further include a buried layer including the P-type dopant located between the well and the semiconductor substrate, and a gate located over the well.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.